Host devices such as computers, laptops, personal video recorders (PVRs), MP3 players, game consoles, servers, set-top boxes, digital cameras, and/or other electronic devices often need to store a large amount of data. Storage devices such as hard disk drives (HDDs) may be used to meet these storage requirements.
A controller communicates with the storage device and the host system. The controller manages interaction between the storage device and the host system. Communication between the host system and the controller is usually provided using one of a variety of standard I/O bus interfaces. Typically, when data is read from a storage device, a host system sends a read command to the controller, which stores the read command into a buffer memory. Data is read from the storage device and stored in a buffer memory.
Conventional controllers use a first-in-first-out (“FIFO”) staging memory for temporarily holding data before data is sent to its proper location. In conventional FIFO implementations, FIFO storage capacity is limited by the size of an address table. An address table identifies the type of data being stored to a FIFO. FIFOs generally consist of a set of read and write pointers and storage and control logic. Referring now to FIG. 1, an exemplary FIFO 10 is shown to include a memory 12 coupled to a write logic 14 and a read logic 16. The memory 12 receives a write enable signal 18. When the write enable signal 18 is asserted, data (not shown), supplied by a write data signal 20, is written to a write address (not shown) in the memory 12. A write address signal 28 provides the write address. Write logic 14 outputs a full signal 22 to a control module (not shown) of the FIFO 10.
The memory 12 receives a read enable signal 24 and outputs data 30 to a first register (not shown). Read logic 16 outputs a read data valid signal 26 to a second register (not shown). The read enable signal 24 requests a read from the FIFO 10, and the read data valid signal 26 serves to denote that new data is accessible on the data bus (not shown) on the following clock cycle. A read address signal 32 indicates the read address to be accessed.